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ltc3705 1 3705fb features descriptio u applicatio s u typical applicatio u isolated 48v telecommunication systems internet servers and routers distributed power step-down converters automotive and heavy equipment high-speed top and bottom gate drivers for 2-switch forward converter on-chip rectifier and self-starting architecture eliminate need for separate gate drive bias supply wide input voltage supply range: 18v to 80v tolerant of 100v input voltage transients linear regulator controller for fast start-up precision uvlo with adjustable hysteresis overcurrent protection volt-second limit prevents transformer core saturation voltage feedforward for fast transient response available in 16-lead narrow ssop package 2-switch forward controller and gate driver the ltc 3705 is a controller for a 2-switch forward converter and includes on-chip bottom and top gate drivers that do not require external transformers. for secondary-side control, combine the ltc3705 with the ltc3706 polyphase secondary-side synchronous forward controller to create a complete forward converter using a minimum of discrete parts. a proprietary scheme is used to multiplex gate drive signals across the isolation barrier through a tiny pulse transformer. the on-chip rectifier and the same pulse transformer provide gate drive bias power. alternatively, the ltc3705 can be used as a standalone voltage mode controller in a primary-side control architec- ture with optoisolator feedback. voltage feedforward pro- vides excellent line regulation and transient response. ndrv gnd pgnd vslmt uvlo boost ltc3705 bas21 fqt7n10 0.22 f 10 f cmpsh1-4 1.2 ? l1 1.2 h tg ts bg is t2 1 f 162k l1: coilcraft ser2010-122 t1: pulse pa0807 t2: pulse pa0297 33nf 30m ? 1w 2m ? 2w si7336adp si7336adp 2 t1 murs120 si7852dp si7852dp murs120 v cc 33nf 15k 365k 100k 2.2 f ss/flt fb/in + fs/in v in v in + 330 f 6.3v 3 2.2 f 680pf czt3019 22.6k 20k 102k v out 3705 ta01 v out + 1 f 100v x3 fg sw sg v in ndrv v cc gnd pgnd phase slp mode regsd pt + i s + i s pt run/ss ltc3706 ith fb fs/sync 36v ?2v to 3.3v/20a isolated 2-switch forward converter , lt, ltc and ltm are registered trademarks of linear technology corporation. polyphase is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. patent pending
ltc3705 2 3705fb power supply (v cc ) ................................... 0.3v to 15v external nmos drive (ndrv) .................... 0.3v to 20v ndrv to v cc ........................................................... 0.3v to 5v bootstrap supply (boost) ...................... 0.3v to 115v top source (ts) .......................................... -5v to 100v boost to ts ............................................. 0.3v to 15v soft-start fault, feedback, frequency set, transformer inputs (ssflt, fb/in + , fs/in ) .................. 0.3v to 15v all other pins (v slmt , i s , uvlo) ................. 0.3v to 5v peak output current <1 s (tg, bg) ........................... 2a operating ambient temperature range .. 40 c to 85 c operating junction temperature (note 2) ............ 125 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, ja = 110 c/w ltc3705egn LTC3705IGN absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v boost = 12v, gnd = pgnd = v ts = 0v, t a = 25 c, unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd i s v slmt uvlo ssflt ndrv fb/in + fs/in ts tg boost nc nc v cc bg pgnd gn part marking 3705 3705i order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ symbol parameter conditions min typ max units v cc supply, linear regulator and trickle charger shunt regulator v ccop operating voltage range 7 12 15 v v cclr output voltage linear regulator in operation 8 v i ndrv current into ndrv pin linear regulator in operation 0.1 1 ma t r(vcc) rise time of v cc linear regulator charging (0.5v to 7.5v) 45 s i ndrvto linear regulator time out current threshold primary-side operation 0.27 ma i cc supply current v uvlo = 1.5v, linear regulator in 1.4 2.1 ma operation (note 3) i ccm maximum supply current v uvlo = 1.5v, trickle charger in operation, 1.7 2.5 ma v cc = 13.2v (note 3) v ccsr maximum supply voltage trickle charger shunt regulator 14.25 15 v i ccsr minimum current into ndrv/v cc trickle charger shunt regulator, v cc = 15v 10 ma (note 3) internal undervoltage v ccuv internal undervoltage threshold v cc rising 5.3 v v cc falling 4.7 v gate drive undervoltage v gduv gate drive undervoltage threshold v cc rising (linear regulator) 7.2 7.4 7.7 v v cc rising (trickle charger) 13.1 13.4 14 v v cc falling 6.8 7.0 7.2 v undervoltage lockout (uvlo) v uvlor undervoltage lockout threshold rising rising 1.220 1.242 1.280 v v uvlof undervoltage lockout threshold falling falling 1.205 1.226 1.265 v
ltc3705 3 3705fb the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v boost = 12v, gnd = pgnd = v ts = 0v, t a = 25 c, unless otherwise noted. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: operating junction temperature t j (in c) is calculated from the ambient temperature t a and the average power dissipation pd (in watts) by the formula: t j = t a + ja ?pd. refer to the applications information section for details. symbol parameter conditions min typ max units i huvlo hysteresis current v uvlo = 1v 4.2 4.9 5.6 a v uvloop voltage feedforward operating range primary-side control v uvlof(min) 3.75 v gate drivers (tg and bg) r os output pull-down resistance i out = 100ma 1.9 ? v oh high output voltage i out = ?00ma 11 v i pu peak pull-up current 1.7 a t r output rise time 10% to 90%, c out = 4.7nf 40 ns t f output fall time 10% to 90%, c out = 4.7nf 70 ns rectifier i rect maximum rectifier dc output current 25 ma oscillator f osc(p) oscillator frequency primary-side control, r fs(p) = 100k ? 200 khz primary-side control, r fs(p) = 25k ? 700 khz primary-side control, r fs(p) = 300k ? 70 khz ? f rfs(p) oscillator resistor set accuracy primary-side control 25k < r fset < 300k 15 % f osc(s) oscillator frequency secondary-side control (during start-up), 300 khz r fs(s) = 100k ? soft-start/fault (ssflt) i ss(c) soft-start charge current primary-side control, v ssflt = 2v 5.2 a secondary-side control, v uvlo = 1.3v, 4 a v ssflt = 2v secondary-side control, v uvlo = 3.75v, 1.6 a v ssflt = 2v v lrto linear regulator time out-threshold 3.9 v v flth fault output high v cc = 8v 6.7 v i ss(d) soft-start discharge current timing out after fault, v ssflt = 2v 1 a current sense input (i s ) v is(max) overcurrent threshold 300 mv volt second limit (v slmt ) v vsl(max) volt-second limit threshold 1.26 v i vslmt(max) maximum volt-second limit resistor current 0.25 ma optoisolator bias current v opto open circuit optoisolator voltage primary-side control i fb = 0v 3.3 v i opto optoisolator bias current primary-side control v fb = 2.5v 0.5 ma primary-side control v fb = 0v 1.6 ma note 3: i cc is the sum of current into ndrv and v cc . note 4: the ltc3705egn is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3705IGN is guaranteed and tested over the 40 c to 85 c operating temperature range.
ltc3705 4 3705fb supply current vs v cc boost current vs boost ?ts voltage uvlo voltage threshold vs temperature uvlo hysteresis current vs temperature oscillator frequency f osc vs r fset oscillator frequency vs temperature shunt regulator current i cc vs v cc shunt regulator current vs temperature v gduv vs temperature typical perfor a ce characteristics uw v cc (v) 0 current (ma) 1.0 1.5 15 3705 g01 0.5 0 10 5 2.0 trickle charger linear regulator v boost ?v ts (v) 0 i boost ( a) 350 300 250 200 150 100 50 15 3705 g02 0 10 5 400 v ts = 0v v ts = 80v r fset (k ? ) 0 f osc (khz) 300 200 100 400 300 200 100 3705 g03 0 800 700 400 500 600 secondary-side control primary-side control v cc (v) 14.00 i cc (ma) 9 6 3 15.00 14.75 14.50 14.25 3705 g04 0 18 12 15 temperature ( c) ?0 uvlo threshold (v) 1.240 1.235 1.230 1.225 100 3705 g09 1.220 40 60 80 0 ?0 20 ?0 1.245 v uvlof v uvlor temperature ( c) ?0 i huvlo ( a) 5.00 4.95 4.90 4.85 100 3705 g10 4.80 40 60 80 0 ?0 20 ?0 5.05 temperature ( c) ?0 oscillator frequency f osc(p) (khz) 202 201 200 199 100 3705 g11 197 198 40 60 80 0 ?0 20 ?0 203 primary-side control r fs(p) = 100k ? temperature ( c) ?0 i ccsr (ma) 100 3705 g12 15 16 17 18 19 40 60 80 0 ?0 20 ?0 25 24 23 22 21 20 temperature ( c) ?0 v gduv (v) 100 3705 g13 6 7 8 40 60 80 0 ?0 20 ?0 14 13 12 11 10 9 v cc rising (trickle charger) v cc rising (linear regulator) v cc falling (both) (t a = 25 c unless otherwise specified)
ltc3705 5 3705fb optoisolator bias v fb/in + vs i fb/in + gate drive pull-down resistance vs temperature gate drive peak pull-up current vs temperature linear regulator start-up gate drive encoding fault operation ? fb/in + (ma) 0 v fb/in + (v) 1.5 1.0 0.5 2.0 1.5 1.0 0.5 3705 g05 0 3.5 2.0 2.5 3.0 5v/div 25 s/div 3705 g06 v in ndrv v cc 10v/div 1 s/div 3705 g07 tg fb/in fs/in 2v/div 10v/div 40ms/div 3705 g08 bg ssflt temperature ( c) ?0 gate drive resistance r os ( ? ) 2.25 2.00 1.75 100 3705 g14 1.50 40 60 80 0 ?0 20 ?0 2.50 temperature ( c) ?0 i pu (a) 1.9 1.8 1.7 1.6 100 3705 g15 1.5 40 60 80 0 ?0 20 ?0 2.0 typical perfor a ce characteristics uw (t a = 25 c unless otherwise specified)
ltc3705 6 3705fb uu u pi fu ctio s gnd (pin 1): signal ground. i s (pin 2): input to the overcurrent comparator. connect to the positive terminal of a current-sense resistor in series with the source of the ground-referenced bottom mosfet. v slmt (pin 3): volt-second limit. form an r-c integrator by connecting a resistor from v in to v slmt and a capacitor from v slmt to ground. the gate drives are turned off when the voltage on the v slmt pin exceeds 1.25v. uvlo (pin 4): undervoltage lockout. connect to a resis- tive voltage divider to monitor input voltage v in . enables converter operation for v uvlo > 1.242v. hysteresis is a fixed 16mv hysteresis voltage with a 4.9 a hysteresis current that combines with the thevenin resistance of the divider to set the total uvlo hysteresis voltage. this input also senses v in for voltage feedforward. finally, this pin can be used for external run/stop control. ssflt (pin 5): combination soft-start and fault indica- tor. a capacitor to gnd sets the duty cycle ramp-up rate during start-up. to indicate a fault, the ssflt pin is momentarily pulled up to within 1.3v of v cc . ndrv (pin 6): drive for the external nmos of the linear regulator. connect to the gate of the nmos and connect a pull up resistor to the input voltage v in . optionally, to create a trickle charger omit the nmos device and connect ndrv to v cc . fb/in + (pin 7): this pin has several functions. the two terminals of one pulse transformer winding are connected to the fb/in + and fs/in pins. the other pulse transformer winding is connected to the ltc3706. the ltc3705 automatically detects when the ltc3706 applies a pulse- encoded signal to the fb/in + and fs/in pins and decodes duty cycle information for control of the primary-side gate drives (see operation below). in secondary-side control, primary-side gate drive bias power is also extracted from the fb/in + and fs/in pins using an on-chip full-wave rectifier. for primary-side control connect this pin to an optoisolator for feedback control of converter output voltage using an internal optoisolator biasing network. fs/in (pin 8): this pin has several functions. place a resistor from this pin to gnd to set the oscillator fre- quency. for secondary-side control with the ltc3706, connect one winding of the pulse transformer for opera- tion as described for the fb/in + pin above. pgnd (pin 9): supply return for the bottom gate driver and the on-chip bridge rectifier. bg (pin 10): bottom gate driver. connect to the gate of the ?ow side?external mosfet. v cc (pin 11): main v cc power for all driver and control circuitry. nc (pins 12, 13): voltage isolation pins. no connection. provided to allow adequate clearance between high-volt- age pins (boost, tg, and ts) and the remainder of the pins. boost (pin 14): top gate driver supply. connect to v cc with a diode to supply power to the ?igh side?external mosfet and bypass with a capacitor to ts. tg (pin 15): top gate driver. connect to the gate of the ?igh side?external mosfet. ts (pin 16): supply return for the top gate driver. connect to the source of the ?igh side?external mosfet.
ltc3705 7 3705fb block diagra w + + + + + + + + 7.4v/7v linear regulator 13.4v/7v trickle charger + 5.3v/4.7v 14.25v 5v soft-start fault regulator + v 0.27ma line off time 4.9 a 0.66 v ff 1.242v 1.226v uvint uvgd 300mv 6 5 2 12 13 4 1 ndrv ssflt uvlo gnd fb/in + fs/in frequency set opto bias rectifier level shift bootstrap refresh pwm receiver condition sw det in + in v cc shunt regulator nc nc is 10 bg 11 v cc 9 pgnd v cc pgnd trickle charge 8v 0.6v 400mv i ndrv uvvin 5v pwm primary control drive logic 15 tg 14 boot 16 ts 3 v slmt oscillator 2v n/c 0v v p-p i osc primary side control pwm secondary control secondary side control 3.3v 7 8 clock ramp v p-p switches on 1.25v oc 3705 bd sw det
ltc3705 8 3705fb mode setting the ltc3705 is a controller and gate driver designed for use in a 2-switch forward converter. when used in con- junction with the ltc3706 polyphase secondary-side synchronous forward controller it forms a complete 2-switch forward converter with secondary-side regula- tion, galvanic isolation between input and output, and synchronous rectification. in this mode, upon start-up, the fb/in + and fs/in pins are effectively shorted by one winding of the pulse transformer. the ltc3705 detects this short circuit to determine that it is in secondary-side control mode. operation in this mode is confirmed when the ltc3706 begins switching the pulse transformer. alternately, the ltc3705 can be used as a standalone primary-side controller. in this case, the fb/in + and fs/in pins operate independently. the fb/in + pin is connected to the collector of an optoisolator to provide feedback and the fs/in pin is connected to the frequency set resistor. gate drive encoding in secondary-side control with the ltc3706, after a start- up sequence, the ltc3706 transmits multiplexed pwm information through a pulse transformer to the fb/in + and fs/in inputs of the ltc3705. in the ltc3705, the pwm receiver extracts the duty cycle and uses it to control the top and bottom gate drivers. figure 1 shows that the ltc3706 drives the pulse trans- former in a complementary fashion, with a duty cycle of approximately 50%. at the appropriate time during the positive half cycle, the ltc3706 applies a short (150ns) zero-voltage pulse across the pulse transformer, indicat- ing the end of the ?n?time. although this scheme allows the transmission of 0% to 50% duty cycle, it is necessary to establish a minimum controllable ?n?time of approxi- mately 100ns. this ensures that 0% duty cycle can be reliably distinguished from 50% duty cycle. on-chip rectifier simultaneously with duty-cycle decoding, and through the same pulse transformer, the near-square-wave gener- ated by the ltc3706 provides primary-side v cc gate drive bias power by way of the ltc3705? on-chip full-wave bridge rectifier. no auxiliary bias supply is necessary and forward converter design and circuitry are considerably simplified. external series pass linear regulator the ltc3705 features an external series pass linear regu- lator that eliminates the long start-up time associated with the conventional trickle charger. the drain of an external nmos is connected to the input voltage and the source is connected to v cc . the gate of the nmos is connected to ndrv. to power the gate, an external pull-up resistor is connected from the input voltage to ndrv. the nmos must be a standard 3v threshold type (i.e. not logic level). an on-chip circuit manages the start up and operation of the linear regulator. it takes approximately 45 s for the linear regulator to charge v cc to its target value of 8v (unless limited by a slower rise of v in ). the ltc3705 begins operating the gate drives when v cc reaches 7.4v. often, the thermal rating of the nmos prevents it from operating continuously, and the ltc3705 ?imes out?the linear regulator to prevent overheating. this is accom- plished using the capacitor connected to the ssflt pin as described subsequently. trickle charger shunt regulator alternately, a trickle charger can be implemented by eliminating the external nmos and connecting ndrv to v cc and using the pull-up resistor to charge v cc . to allow extra headroom for starting, the ltc3705 detects this mode and increases the threshold for starting the gate drives to 13.4v. an internal shunt regulator limits the voltage on the trickle charger to 15v. operatio u figure 1. gate drive multiplexing scheme duty cycle = 15% duty cycle = 0% 150ns 150ns 150ns 1 clk per 1 clk per +7v ?v v pt1 + ?v pt1
ltc3705 9 3705fb self-starting architecture the ltc3705 is combined with the ltc3706 to form a complete self-starting dc isolated power supply. when power is first applied, and when v cc for the ltc3705 is above the appropriate threshold, the ltc3705 begins open-loop operation using its own internal oscillator. power is supplied to the secondary by switching the gate drivers with a gradually increasing duty cycle as controlled by the rate of rise of the voltage on the ssflt pin. a peak detector power supply for the ltc3706 allows it to begin operation even for small duty cycles. once adequate voltage is available for the ltc3706, it provides duty cycle information and gate drive bias power using the pulse transformer as shown in figure 1. the ltc3705 detects the appearance of this signal and transfers control of the gate drivers to the ltc3706. simultaneously, the ltc3705 also enables the on-chip rectifier and turns off the linear regulator. alternately, when the ltc3705 is used as a standalone primary-side controller, the gradually increasing duty cycle powers up a secondary-side reference and optoisolator and feedback is accomplished when the output of the optoisolator begins pulling down in the fb/in + pin. soft-start and fault these two functions are implemented using the ssflt pin. (this pin is also used for linear regulator timeout as described in the following section.) initiating soft-start requires that: 1) the gate drive undervoltage (uvgd) goes low meaning that adequate voltage is available on the v cc pin (7.4v for the linear regulator or 13.4v for the trickle charger) and 2) the input undervoltage (uvv in ) goes low meaning that the voltage on the uvlo pin has reached the 1.242v rising threshold. during soft-start, the ltc3705 gradually charges the soft- start capacitor to ramp up the converter duty cycle. soft- start is over when the voltage on the ssflt pin reaches 2.8v. in normal operation, at some point before this, the ltc3705 makes a transition to controlling duty cycle using closed- loop regulation of the converter output voltage. the ssflt pin is also used to indicate a fault. the ltc3705 recognizes faults from four origins: 1) an overcurrent fault caused by the current sense voltage on the is pin exceed- ing the 300mv overcurrent threshold, 2) an input undervoltage fault caused by the uvlo pin falling below the 1.226v falling threshold, 3) a gate drive undervoltage fault caused by the voltage on the v cc pin falling below the 7v threshold, or 4) loss of the gate drive encoding signal from the ltc3706. upon sensing a fault, the ltc3705 immediately turns off the top and bottom gate drives and indicates a fault by quickly pulling the voltage on the ssflt pin to within 1.3v of the voltage on the v cc pin. after indicating the fault, the ltc3705 quickly ramps down the voltage on the ssflt pin to approximately 2.8v. then, to allow complete dis- charge of the secondary-side circuit, the ltc3705 slowly ramps down the voltage on the ssflt pin to about 200mv. the ltc3705 then attempts a restart. linear regulator timeout the thermal rating of the linear regulator? external nmos often cannot allow it to indefinitely supply bias current to the primary-side gate drives. the ltc3705 has a linear regulator timeout mechanism that also uses the ssflt capacitor. as described in the prior section, soft-start is over once the voltage on the ssflt pin reaches 2.8v. however, the ssflt capacitor continues to charge and the linear regu- lator is turned off when the voltage on the ssflt pin reaches 3.9v. the ?pplications information?section de- scribes linear regulator timeout in more detail. volt-second limit the volt-second limit ensures that the power transformer core does not saturate for any combination of duty cycle and input voltage. the input of an r-c integrator is connected to v in and its output is connected to the v slmt pin. while the top and bottom gate drives are ?ff,?the ltc3705 grounds the v slmt pin. when the gate drives are turned ?n?the v slmt pin is released and the capacitor is allowed to charge in proportion to v in . if the capacitor voltage on the v slmt pin exceeds 1.25v the two gate drives are immediately turned ?ff.?note that this is not considered a fault condition and the ltc3705 can run indefinitely with the switch duty cycle being determined by operatio u
ltc3705 10 3705fb uvlo the uvlo pin is connected to a resistive voltage divider connected to v in as shown in figure 2. the voltage threshold on the uvlo pin for v in rising is 1.242v. to introduce hysteresis, the ltc3705 draws 4.9 a from the uvlo pin when v in is rising. the hysteresis is therefore user adjustable and depends on the value of r1. the uvlo threshold for v in rising is: vv rr r ra in uvlo rising (, ) (. ) (. ) = + + 1 242 12 2 149 the volt-second limit circuit. the duty cycle is always limited to 50% to ensure that the power transformer flux always has time to reset before the start of the next cycle. in an alternate application, the volt-second limit can be used for open-loop regulation of the output against changes in v in . current limit current limit for the ltc3705 is principally a safety feature to protect the converter and is not part of a control function. the current that flows in series through the top switch, the transformer primary, and the bottom switch is sensed by a resistor connected between the source of the bottom switch and gnd. if the voltage across this resistor exceeds 300mv, the ltc3705 initiates a fault. bootstrap refresh the ltc3705 incorporates a unique bootstrap refresh circuit to ensure that the bootstrap supply (boost) for the top switch has adequate voltage for operation at low duty cycles. therefore, the ltc3705 does not require a undervoltage lockout for the bootstrap supply and a po- tential source of unexpected shutdowns is eliminated. voltage feedforward the ltc3705 uses voltage feedforward to properly modu- late the duty cycle as a function of the input voltage. for secondary-side control with the ltc3706, voltage feedforward is used during start-up only. the duty cycle during start up is determined by comparison of the voltage on the ssflt pin to a 50% duty cycle triangle wave with an amplitude of 2v. to implement voltage feedforward, the charging current for the soft-start capacitor is reduced in proportion to the input voltage. as a result, the initial rate of rise of the converter output voltage is held approxi- mately constant regardless of the input voltage. at some point during start-up, the ltc3706 begins to switch the pulse transformer and takes over the soft-start. for operation with standalone primary-side control and optoisolator feedback, voltage feedforward is used during both start-up and normal operation. the duty cycle is determined by using a 50% duty cycle triangle wave with an amplitude equal to 66% of the voltage on the uvlo pin which is, in turn, proportional to v in . the charging current for the soft-start capacitor is a constant 5.2 a. during soft-start, the duty cycle is determined by comparing the voltage on the ssflt pin to the triangle wave. soft-start is concluded when the voltage on the ssflt pin exceeds the voltage on the fb/in + pin. after the conclusion of soft- start, the duty cycle is determined by comparison of the voltage on the fb/in + pin to the triangle wave. optoisolator bias when the ltc3705 is used in standalone primary-side mode, feedback is provided by an optoisolator connected to the fb/in + pin. the ltc3705 has a built optoisolator bias circuit which eliminates the need for external components. operatio u applicatio s i for atio wu uu the ltc3705 also has 16mv of voltage hysteresis on the uvlo pin so that the uvlo threshold for v in falling is: vv rr r in uvlo falling (, ) (. ) = + 1 226 12 2 to implement external run/stop control, connect a small nmos to the uvlo pin as shown in figure 2. turning the nmos on grounds the uvlo pin and prevents the ltc3705 from running.
ltc3705 11 3705fb completes the soft-start interval. in order to ensure that control is properly transferred from the ltc3705 (pri- mary-side) to the ltc3706 (secondary-side), it is neces- sary to limit the rate of rise on the primary-side soft-start ramp so that the ltc3706 has adequate time to wake up and assume control before the output voltage gets too high. this condition is satisfied for many applications if the following relationship is maintained: c ss,sec c ss_pri however, care should be taken to ensure that soft-start transfer from primary-side to secondary-side is com- pleted well before the output voltage reaches its target value. a good design goal is to have the transfer completed when the output voltage is less than one-half of its target value. note that the fastest output voltage rise time during primary-side soft-start mode occurs with minimum load current. the open-loop start-up frequency on the ltc3705 is set by placing a resistor r fs(s) from the fs/in pin to gnd. although the exact start-up frequency on the primary side is not critical, it is generally a good practice to set it approximately equal to the operating frequency on the secondary side. in this mode the start-up frequency of the ltc3705 is approximately: f r pri fs s = + 34 109 10 000 , () in the event that the ltc3706 fails to start up properly and assume control of switching, there are several fail-safe mechanisms to help avoid overvoltage conditions. first, the ltc3705 implements a volt-second clamp that may be used to keep the primary-side duty cycle at a level that does not produce an excessive output voltage. second, the timeout of the linear regulator (described in the follow- ing section) means that, unless the ltc3706 starts and supports the ltc3705? gate drives through the pulse transformer and on-chip rectifier, the ltc3705 eventually suffers a gate drive undervoltage fault. finally, the ltc3706 has an independent overvoltage detection circuit that crowbars the output of the dc/dc converter using the synchronous secondary-side mosfet switch. applicatio s i for atio wu u u figure 2. resistive voltage divider for uvlo and optional run/stop control r1 r2 v in run/stop control (optional) uvlo gnd ltc3705 3705 f02 linear regulator the linear regulator eliminates the long start-up times associated with a conventional trickle charger by using an external nmos to quickly charge the capacitor connected to the v cc pin. note that a trickle charger usually requires a large capaci- tor to provide holdup for the v cc pin while the converter attempts to start. the linear regulator in the ltc3705 can both charge the capacitor connected to the v cc pin and provide primary-side gate-drive bias current. therefore, with the linear regulator, the capacitor need only be large enough to cope with the ripple current from driving the top and bottom gates and holdup need not be considered. the external nmos for the linear regulator should be a standard 3v threshold type (i.e. not a logic level thresh- old). the rate of charge of v cc from 0v to 8v is controlled by the ltc3705 to be approximately 45 s regardless of the size of the capacitor connected to the v cc pin. the charging current for this capacitor is approximately: i v s c c = 8 45 the safe operating area (soa) for the external nmos should be chosen so that capacitor charging does not damage the nmos. excessive values of capacitor are unnecessary and should be avoided. start-up considerations when used in a self-starting converter with the ltc3706, the ltc3705 initially begins the soft-start of the converter in an open-loop fashion. after bias is obtained on the secondary side, the ltc3706 assumes control and
ltc3705 12 3705fb in the event that a short-circuit is applied to the output of the converter prior to start-up, the ltc3706 generally does not receive enough bias voltage to operate. in this case, the ltc3705 detects a fault for one of two reasons: 1) since the ltc3706 never sends pulse encoding to the ltc3705, the linear regulator times out resulting in a gate drive undervoltage fault, or 2) the primary-side overcurrent circuit is tripped because of current buildup in the output inductor. in either case, the ltc3705 initiates a shutdown followed by a soft-start retry. linear regulator timeout after start-up, the ltc3705 times out the linear regulator to prevent overheating of the external nmos. the timeout interval is set by further charging the soft-start capacitor c ssflt from the end-of-soft-start voltage of approximately 2.8v to the timeout threshold of 3.9v. linear regulator timeout behaves differently depending on mode. in primary-side standalone mode, the ltc3705 generally requires that an auxiliary gate drive bias supply take over from the linear regulator. (see the subsequent section for more detail on the auxiliary supply.) during linear regula- tor timeout, the rate of rise of the soft-start capacitor voltage depends on the current into the ndrv pin as controlled by the pull-up resistor r pullup , the value of v in and the value of v ndrv . i vv r ndrv in ndrv pullup = the value of v ndrv is v cc = 8v plus the value of the gate- to-source voltage (v ndrv ?v cc ) of the external nmos in the linear regulator. the gate-to-source voltage depends on the actual device but is approximately the threshold voltage of the external nmos. for i ndrv > 0.27ma, the capacitor on the ssflt pin is charged in proportion to (i ndrv ?0.27ma) until the linear regulator times out. thus, since v ndrv is very nearly constant, the timeout interval for the linear regulator is inversely proportional to the input voltage and a higher input voltage produces a shorter timeout. t cvv vv r ma timeout ssflt in ndrv pullup = ? ? ? ? ? ? ? 66 39 28 027 (. . ) ? since the power dissipation of the linear regulator is proportional to the input voltage, this strategy of making the timeout inversely proportional to the input voltage produces an approximately constant temperature excur- sion for the external nmos of the linear regulator regard- less of the input voltage. in situations for which the continuous operation of the linear regulator does not exceed the thermal limitations of the external nmos (i.e. converters with low v in or with minimal gate drive bias requirements), the auxiliary sup- ply can be omitted and the linear regulator allowed to operate continuously. if i ndrv is less than 0.27ma the linear regulator never times out and the voltage on the ssflt pin stays at approximately 2.8v after start-up is completed. to accomplish this set: r vv ma pullup in max ndrv > () . 027 where v in(max) is the maximum expected continuous input voltage. note that once the linear regulator is turned off it locks out. therefore when using this strategy, care should be taken to ensure that a transient higher than v in(max) does not persist longer than t timeout . in secondary-side operation with the ltc3706, there is never any need for continuous operation of the linear regulator since gate drive bias power is provided by the ltc3706 through the pulse transformer and on-chip rectifier. the ltc3705 shuts down the linear regulator once the ltc3706 begins switching the pulse trans- former. if the ltc3706 fails to start, the ltc3705 quickly times out the linear regulator once the voltage on the ssflt pin reaches 2.8v. fault lockout the ltc3705 indicates a fault by pulling the ssflt pin to within 1v of v cc . the ltc3705 subsequently attempts a restart. optionally, the user can prevent restart and ?ock out?the converter by clamping the voltage on the ssflt pin with a 4.3v zener diode. once the converter has locked out it can only be restarted by the removal of the input voltage or by release of the zener diode clamp. applicatio s i for atio wu uu
ltc3705 13 3705fb applicatio s i for atio wu uu pulse transformer the pulse transformer that connects the ltc3706 to the ltc3705 performs the dual functions of gate drive duty cycle encoding and gate drive bias supply for the ltc3705 by way of the on-chip full-wave rectifier. the designs of the ltc3705 and ltc3706 have been coordinated so that the transformer turn ratio is: n ltc3705 = 2n ltc3706 where n ltc3705 is the number of turns in the winding connected to the fb/in + and fs/in pins of the ltc3705 and n ltc3706 is the number of turns in the winding connected to the pt + and pt pins of the ltc3706. the winding connected to the ltc3706 must be able to with- stand volt-seconds equal to: () vs v f max cc = 2 where v cc is the maximum supply voltage for the ltc3706 and f is the operating frequency of the ltc3706. auxiliary supply when used with the ltc3706, the ltc3705 does not require an auxiliary supply to provide primary-side gate- drive bias current. after start-up, primary-side gate drive current is provided by the ltc3706 through a small pulse transformer and the ltc3705? on-chip rectifier. however, when used as a standalone primary-side con- troller, the ltc3705 may require a conventional gate-drive bias supply as shown in figure 3. the bias supply must be designed to keep the voltage on the v cc pin between the absolute maximum of 15v and the gate-drive undervoltage lockout of 7v. the auxiliary supply is connected in parallel with v cc . the linear regulator maintains v cc at 8v. if the auxiliary supply produces more than 8v, it turns off the external nmos before the ltc3705 can time out the linear regulator. if the auxiliary supply produces less than 8v, the linear regulator times out and then the voltage on the v cc pin declines to the voltage produced by the auxiliary supply. slave mode operation when the ltc3705 is paired with the ltc3706, multiple pairs can be used to form a polyphase converter. in polyphase operation, one ltc3705 becomes the ?aster while the remainder become ?laves.?the master con- trols start-up in the same manner as for the single-phase converter, while the slaves do not begin switching until receiving pwm information through their own pulse trans- former from their corresponding ltc3706. to synchro- nize operation, the ssflt and v cc pins of the master are connected to the corresponding pins of all the slaves. the master is designated by connection of the frequency set resistor to the fs/in pin while this resistor is omitted from the slaves. for the slaves the ndrv pin is connected to the v cc pin. see the following section on polyphase applica- tions for more detail. polyphase applications figure 4 shows the basic connections for using the ltc3705 and ltc3706 in polyphase applications. one of the phases is always identified as the ?aster,? while all other phases are ?laves.?for the ltc3705 (primary side), the master performs the open-loop start-up and supplies the initial v cc voltage for the master and all slaves. the ltc3705 slaves are put into that mode by omitting the resistor on fs/in? the ltc3705 slaves simply stand by and wait for pwm signals from their respective pulse transformers. since the ssflt pins of master and slave ltc3705s are interconnected, a fault (overcurrent, etc.) on any one of the phases will perform a shutdown/restart on all phases together. power transformer 2.2 f primary winding n p secondary winding n s bas21 bas21 1mh v in ltc3705 3705 f03 ndrv v cc gnd auxiliary winding n a figure. 3. auxiliary supply for primary-side control
ltc3705 14 3705fb grounding considerations the lt3705 is typically used in high current converter designs that involve substantial switching transients. fig- ure 5 illustrates these currents. the switch drivers on the ic are designed to drive large capacitances and, as such, generate significant transient currents. careful consider- ation must be made regarding input and local power supply bypassing to avoid corrupting the ground refer- ences used by the uvlo and frequency set circuitry. typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from gnd. by virtue of the topologies used in lt3705 applications, the large currents from the primary switches, as well as the switch drive transients, pass through the sense resistor to ground. this defines the ground connec- tion of the sense resistor as the reference point for both gnd and pgnd. effective grounding can be achieved by considering the return current paths from the sense resistor to each respective bypass capacitor. don? be tempted to run small traces to separate the grounds. a power ground plane is important as always in high power converters, but care must be taken to keep high current paths away from the gnd reference. an effective approach is to use a 2- layer ground plane, reserving an entire layer for gnd and an entire layer for pgnd. the uvlo and frequency set resistors can then be directly connected to the gnd plane. for the ltc3706, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the i th pins. faults and shutdowns are communicated via the interconnection of the run/ss pins. the ltc3706 is put into slave mode by tying the fb pin to v cc . standalone primary-side operation the ltc3705 can be used to implement a standalone forward converter using optoisolator feedback and a secondary-side voltage reference. alternately the ltc3705 can be used to implement an open-loop forward converter using the vslmt pin to regulate against changes in v in . in either case, the ltc3705 oscillator determines the fre- quency as found from: f r osc fs p = + 21 10 4200 9 () note that polyphase operation is not possible in the stand- alone configuration. applicatio s i for atio wu uu
ltc3705 15 3705fb applicatio s i for atio wu uu ndrv uvlo ltc3705 (master) v cc ss/flt fb/in + fs/in v in v in + v in ndrv v cc pt + pt run/ss ltc3706 (master) ith 3705 f04 v out + v bias fb fs/sync ndrv ss/flt ltc3705 (slave) v cc uvlo fb/in + fs/in v in ndrv v cc pt + pt run/ss ltc3706 (slave) ith fb phase fs/sync figure 4. connections for polyphase
ltc3705 16 3705fb figure 5. high-current transient return paths lt3705 fs/in gnd v boost signal ground plane power ground plane boost v in v in ts tg bg v cc v cc pgnd uvlo 3705 f05 applicatio s i for atio wu uu
ltc3705 17 3705fb typical applicatio s u ndrv gnd pgnd vslmt uvlo boost ltc3705 bas21 fqt7n10 0.22 f 2.2nf 250v 1nf 100v 1nf 100v 10 f 25v cmpsh1-4 1.2 ? l2 1.2 h 10 ? 0.25w 10 ? 0.25w tg ts bg is t2 1 f 162k l1: vishay ihlp-2525cz-01 l2: coilcraft ser2010-122 t1: pulse pa0807 t2: pulse pa0297 33nf 30m ? 1w 2m ? 2w si7336adp si7336adp 2 t1 2:1 9:2 murs120 murs120 v cc 33nf 1nf 15k 1% 365k 1% 100k 2.2 f 25v ss/flt fb/in + fs/in v in v in + l1 1 h 330 f 6.3v 3 1 f 2.2 f 16v 470pf 680pf fg sw sg v in ndrv czt3019 v cc gnd pgnd phase slp mode regsd pt + i s + i s pt run/ss ltc3706 ith 22.6k 1% 100k 20k 680pf 102k 1% v out 3705 f06 v out + fb fs/sync 0.1 f 5k 1nf 1 f 100v 1 f 100v x3 100 ? 100 ? 100 ? 100 ? si7852dp si7852dp figure 6. 36v-72v to 3.3v/20a isolated forward converter using ltc3706 load current (a) 0 85 90 95 20 15 3705 f06c 510 25 80 efficiency (%) v in = 36v v in = 72v 20 s/div v in = 48v v out = 3.3v load step = 0a to 20a v out 50mv/div i out 10a/div 3705 f06b efficiency load step
ltc3705 18 3705fb 1mh do1608c-105 l1 25 h bas21 murs120 t1 pa0520 ndrv gnd v slmt ltc3705 i s fb/in + fs/in uvlo ssflt 6 1 3 2 7 8 4 5 11 16 14 15 10 9 13 12 v cc ts boot bg tg pgnd nc nc p2 v in v in + 36v to 72v v out v out + 12v 5a l2 0.82 h 1 f 100v 1 f 100v 270pf 0.033 f 1000pf 470pf iso1 moc207 0.22 f 330pf 301k 100 ? 100k 365k 1% r16 0.025 ? 1w 15k 1% 301k 10 ? 10 ? q1 0.1 f 2.2 f 25v fqt7n10 c7: tpse686m025r0125 avx d1a, d1b: mbrb20100ct d3: p6smb15at3 l1: gowanda 050km2502sm l2: vishay ihlp2525czerr82m01 q1, q2: siliconix si7456dp + 1 f 100v 2.2nf 250v q2 murs120 bas21 bas21 d1b d3 d1a c21 330pf 200v r36 20 ? 1w c7 68 f 2x 10nf 10nf 2k 2.49k 9.53k 160 ? 1 6 27 511 8t 5t 6t 11 7 col v + lt1431 1 3 8 6 5 ref gndf gnds 0.047 f 1k + 3705 f07 mmbt2907a mmbt2907a 0.1 f typical applicatio s u figure 7. 36v-72v to 12v/5a isolated forward converter using optoisolator current (a) 0 86 84 82 88 90 92 4 3 3705 f07c 12 5 80 efficiency (%) v in = 36v v in = 48v v in = 72v efficiency
ltc3705 19 3705fb gn16 (ssop) 1005 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
ltc3705 20 3705fb part number description comments ltc1693 high speed single/dual n-channel mosfet drivers cmos compatible input, v cc range: 4.5v to 12v ltc1698 secondary synchronous rectifier controller use with the lt1681, optocoupler driver, pulse transformer synchronization lt1950 single switch controller used for 20w to 500w forward converters ltc3706 polyphase secondary-side synchronous fast transient response, self-starting architecture, current mode control forward controller lt3710 secondary-side synchronous post regulator for regulated auxiliary output in isolated dc/dc converters lt3781 ?ootstrap?start dual transistor synchronous 72v operation, synchronous switch output forward controller lt3804 secondary side dual output controller regulates two secondary outputs, optocoupler feedback driver with opto driver and second output synchronous driver controller ltc3901 secondary-side synchronous driver for similar function to ltc3900, used in full-bridge and push-pull converter push-pull and full-bridge converter ltc4440/ltc4440-5 high speed, high voltage and high side high side source up to 100v, up to 15v gate drive supply, 6-lead gate drivers thinsot tm or 8-lead exposed pad msop packages ltc4441 6a mosfet driver adjustable gate drive from 5v to 8v, 5v to 28v v in range thinsot is a trademark of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1006 rev b ?printed in usa related parts figure 8. 36v-72v to 12v/5a open-loop regulated isolated forward converter using vslmt 15v 1mh do1608c-105 l1 25 h bas21 murs120 t1 pa0520 ndrv gnd v slmt ltc3705 i s fb/in + fs/in uvlo ssflt 6 1 3 2 7 8 4 5 11 16 14 15 10 9 13 12 v cc ts boot bg tg pgnd nc nc p2 v in p1 v in + 36v to 72v p3 v out p4 v out + 12v 5a l2 0.82 h 1 f 100v 1 f 100v 220pf 0.033 f 1000pf 0.22 f 330pf 301k 100 ? 100k 365k 1% 0.025 ? 1w 15k 1% 301k 10 ? 10 ? q1 0.1 f 2.2 f 25v fqt7n10 c7: tpse686m025r0125 avx d1a, d1b: mbrb20100ct d3: p6smb15at3 l1: gowanda 050km2502sm l2: vishay ihlp2525czerr82m01 q1, q2: siliconix si7456dp + 1 f 100v 2.2nf 250v q2 murs120 bas21 bas21 d1b d3 d1a 330pf 200v 20 ? 1w c7 68 f 2x 1 6 27 511 8t 5t 6t 11 7 + 3705 f08 mmbt2907a mmbt2907a 0.1 f load (a) 0 8 6 4 2 14 12 10 16 18 4 3 3705 f08b 12 5 0 output voltage (v) v in = 36v v in = 48v v in = 72v regulation u typical applicatio

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